Texas Instruments SN74LVC1G34DCKT Non-Inverting Buffer, 5-Pin SC-70
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer
Number of Channels
1
Schmitt Trigger Input
No
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
4.1 ns @ 3.3 V
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Temperature
-40 °C
Height
0.9mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+85 °C
Length
2mm
Width
1.25mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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EGP 22.59
Each (Supplied on a Reel) (ex VAT)
Production pack (Reel)
5
EGP 22.59
Each (Supplied on a Reel) (ex VAT)
Production pack (Reel)
5
Ideate. Create. Collaborate
JOIN FOR FREE
No hidden fees!
- Download and use our DesignSpark software for your PCB and 3D Mechanical designs
- View and contribute website content and forums
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Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer
Number of Channels
1
Schmitt Trigger Input
No
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
4.1 ns @ 3.3 V
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Temperature
-40 °C
Height
0.9mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+85 °C
Length
2mm
Width
1.25mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
Ideate. Create. Collaborate
JOIN FOR FREE
No hidden fees!
- Download and use our DesignSpark software for your PCB and 3D Mechanical designs
- View and contribute website content and forums
- Download 3D Models, Schematics and Footprints from more than a million products