Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Signal Type
Single Ended
Triggering Type
Positive Edge
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
6
Set/Reset
Reset
Number of Elements per Chip
1
Maximum Propagation Delay Time @ Maximum CL
5.7 ns @ 3.3 V
Dimensions
2.9 x 1.6 x 1.15mm
Maximum Operating Supply Voltage
5.5 V
Height
1.15mm
Width
1.6mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2.9mm
Country of Origin
Thailand
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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EGP 46.63
Each (On a Reel of 250) (ex VAT)
250
EGP 46.63
Each (On a Reel of 250) (ex VAT)
250
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Signal Type
Single Ended
Triggering Type
Positive Edge
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
6
Set/Reset
Reset
Number of Elements per Chip
1
Maximum Propagation Delay Time @ Maximum CL
5.7 ns @ 3.3 V
Dimensions
2.9 x 1.6 x 1.15mm
Maximum Operating Supply Voltage
5.5 V
Height
1.15mm
Width
1.6mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2.9mm
Country of Origin
Thailand
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22