Technical Document
Specifications
Brand
NexperiaLogic Family
74LVT
Logic Function
Bus Transceiver
Number of Elements per Chip
2
Number of Channels per Chip
16
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
48
Input Level
TTL
Output Level
TTL
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
64mA
Maximum Propagation Delay Time @ Maximum CL
3.5 ns, 4.6 ns, 5.1 ns, 5.3 ns, 5.7 ns
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+85 °C
Length
12.6mm
Maximum Operating Supply Voltage
3.6 V
Height
1.05mm
Width
6.2mm
Dimensions
12.6 x 6.2 x 1.05mm
Minimum Operating Supply Voltage
2.7 V
Propagation Delay Test Condition
50pF
Product details
74LVT Family, Nexperia
Low-Voltage BiCMOS Technology Logic
Operating Voltage 2.7 to 3.6
Compatibility: Input LVTTL/TTL, Output LVTTL
74LVT Family
EGP 775.70
EGP 77.57 Each (Supplied as a Tape) (ex VAT)
Standard
10
EGP 775.70
EGP 77.57 Each (Supplied as a Tape) (ex VAT)
Standard
10
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Technical Document
Specifications
Brand
NexperiaLogic Family
74LVT
Logic Function
Bus Transceiver
Number of Elements per Chip
2
Number of Channels per Chip
16
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
48
Input Level
TTL
Output Level
TTL
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
64mA
Maximum Propagation Delay Time @ Maximum CL
3.5 ns, 4.6 ns, 5.1 ns, 5.3 ns, 5.7 ns
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+85 °C
Length
12.6mm
Maximum Operating Supply Voltage
3.6 V
Height
1.05mm
Width
6.2mm
Dimensions
12.6 x 6.2 x 1.05mm
Minimum Operating Supply Voltage
2.7 V
Propagation Delay Test Condition
50pF
Product details
74LVT Family, Nexperia
Low-Voltage BiCMOS Technology Logic
Operating Voltage 2.7 to 3.6
Compatibility: Input LVTTL/TTL, Output LVTTL