Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Type
3 State
Output Signal Type
Single Ended
Triggering Type
Positive Edge
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
20
Number of Elements per Chip
8
Maximum Propagation Delay Time @ Maximum CL
3.6 ns @ 2.7 V
Dimensions
6.6 x 4.5 x 0.95mm
Maximum Operating Supply Voltage
3.6 V
Height
0.95mm
Width
4.5mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+125 °C
Propagation Delay Test Condition
50pF
Length
6.6mm
Product details
74LVC Family Flip-Flops & Latches, Nexperia
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
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EGP 12.44
Each (In a Tube of 75) (ex VAT)
75
EGP 12.44
Each (In a Tube of 75) (ex VAT)
75
Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Type
3 State
Output Signal Type
Single Ended
Triggering Type
Positive Edge
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
20
Number of Elements per Chip
8
Maximum Propagation Delay Time @ Maximum CL
3.6 ns @ 2.7 V
Dimensions
6.6 x 4.5 x 0.95mm
Maximum Operating Supply Voltage
3.6 V
Height
0.95mm
Width
4.5mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+125 °C
Propagation Delay Test Condition
50pF
Length
6.6mm
Product details
74LVC Family Flip-Flops & Latches, Nexperia
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS